Download e-book for iPad: Algorithms and Architectures for Parallel Processing: 8th by Hong Shen (auth.), Anu G. Bourgeois, S. Q. Zheng (eds.)

By Hong Shen (auth.), Anu G. Bourgeois, S. Q. Zheng (eds.)

ISBN-10: 3540695001

ISBN-13: 9783540695004

ISBN-10: 354069501X

ISBN-13: 9783540695011

This publication constitutes the refereed court cases of the eighth foreign convention on Algorithms and Architectures for Parallel Processing, ICA3PP 2008, held in Agia Napa, Cyprus, in June 2008.

The 31 revised complete papers awarded including 1 keynote speak and 1 educational have been rigorously reviewed and chosen from 88 submissions. The papers are prepared in topical sections on scheduling and cargo balancing, interconnection networks, parallel algorithms, disbursed structures, parallelization instruments, grid computing, and software program systems.

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We can clearly see that upcoming technologies have introduced a totally new class of architectural systems that are very heterogeneous in terms of computational power and network connectivity. Most of the graph partitioning algorithms mentioned above compute a data partitioning that is suitable for homogeneous environments only. Recently there has been some work on partitioning for heterogeneous architectures, namely PaGrid [16, 24], JOSTLE [22], MiniMax [21], and DRUM [6]. In the context of the widely used MeTiS [17] library, we have developed graph partitioning algorithms for partitioning meshes/graphs onto heterogeneous architectures.

Morana and storage nodes, but also the underlying networks connecting them are heterogeneous. Fig. 1 shows a typical example of grid deployment. In this type of hierarchical organization it is possible to identify three scheduling layers. The first one is related to the algorithm used by RB to distribute jobs among CEs; this algorithm influences in a strong manner the performance of the whole system. The second scheduling layer manages the jobs allocation done by the CE on its underlying WNs. Finally lowest scheduling activity is related to the mechanism used by the operating system(OS) of each WN to schedule jobs on its CPU.

Expected makespans of example 1 1000 A Static Multiprocessor Scheduling Algorithm 27 Processor 3: n3 ; Processor 4: n6 . Note that the schedules DCP-1, DCP-2 and UIS-1 are all optimal schedules under determinate costs assumption, but they perform differently when costs have uncertainty. 41. Example 2. In the second example, one processor in target system is heterogeneous and a little faster than the other three. Without lose of generality, we assume that Processor 1 is a little faster. The computation costs on this processor are listed in Table 3.

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Algorithms and Architectures for Parallel Processing: 8th International Conference, ICA3PP 2008, Cyprus, June 9-11, 2008 Proceedings by Hong Shen (auth.), Anu G. Bourgeois, S. Q. Zheng (eds.)


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